This week, a breadboard, wire, and IC logic gates were obtained and wiring for the clock display was begun.
A setback was run into when it was found that the university could only supply us with AND, NOR, NOT, and NAND gates. The initial logic was designed using AND, OR, and NOT gates, and the lack of OR gates proved tedious to overcome.
We began considering alternatives to the described system, such as using a combination of multiplexers, decoders, and digital flip-flops. If this system is implemented, then only 5 outputs will have to be used, instead of 12.
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